Embedded Boundary Scan Controller (Ieee 1149.1 Support)
- Compatible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture
- Supported by Fairchild's SCAN Ease (Embedded Application Software Enabler) Software
- Uses generic, asynchronous processor interface; compatible with a wide range of processors and PCLK frequencies
- Directly supports up to two 1149.1 scan chains
- 16-bit Serial Signature Compaction (SSC) at the Test Data In (TDI) port
- Automatically produces pseudo-random patterns at the Test Data Out (TDO) port
- Fabricated on FACT™ 1.5 µm CMOS process
- Supports 1149.1 test clock (TCK) frequencies up to 25 MHz
- TTL-compatible inputs; full-swing CMOS outputs with 24 mA source/sink capability
SCANPSC100FSC
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